CY7C140 查看數據表（PDF） - Cypress Semiconductor

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CY7C140

1K x 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Busy Timing Diagram No. 1 (CE Arbitration)

CEL Valid First:

ADDRESS LR,

ADDRESS MATCH

CEL

CER

tPS

BUSYR

tBLC

tBHC

CER Valid First:

ADDRESSL,R

CER

ADDRESS MATCH

CEL

tPS

BUSYL

tBLC

tBHC

Busy Timing Diagram No. 2 (Address Arbitration)

Left Address Valid First:

ADDRESSL

tRC or tWC

ADDRESS MATCH

tPS

ADDRESS MISMATCH

ADDRESSR

BUSYR

tBLA

tBHA

Right Address Valid First:

ADDRESSR

tRC or tWC

ADDRESS MATCH

tPS

ADDRESSL

tBLA

BUSYL

ADDRESS MISMATCH

tBHA

CY7C130/CY7C131

CY7C140/CY7C141

Document #: 38-06002 Rev. *D

Page 10 of 19

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