CY7C1300A 查看數據表（PDF） - Cypress Semiconductor

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CY7C1300A

128K X 36 Dual I/O Dual Address Synchronous SRAM

Cypress Semiconductor 

Switching Waveforms (continued)[22]

CY7C1300A

Write Cycle Timing to Both Ports (PTX, PTY HIGH)[21]

tKC

tKL

CLK

tKH

AX 1

2

3

4

5

6

PORT X

WEX#

OEX#

tH

tS

tH

tS

DQX

D(2) D(3) D(4)

CE#

(See Note)

AY 12 13 14 15

5

6

7

8

9

D(8) D(9)

tS

tH

18 19 20

PORT Y

WEY#

OEY#

DQY

D(14) D(15) D(5) D(6) D(18) D(19)

PORT Y TAKES

PRIORITY OVER PORT X

WHEN AX=AY AND

WRITING TO BOTH

Document #: 38-05075 Rev. *C

Page 8 of 12

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