AD7390ARZ-REEL7 查看數據表（PDF） - Analog Devices

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AD7390ARZ-REEL7

3 V Serial-Input Micropower 10-Bit and 12-Bit DACs

Analog Devices 

AD7390/AD7391

SDI

CLK

LD

SDI

CLK

LD

CLR

FS

VOUT

ZS

D11

D10

D9

D7

AD7390 AD7391

tLD1

tLD1

D5

D4

D3

D2

D1

D0

tLD2

DAC REGISTER LOAD

tDS

tCL

tDH

tCH

tLDW

tS

Figure 4. Timing Diagram

0.1% FS

ERROR BAND

tCLRW

tS

CLK CLR LD

↑

H

H

X

H

L

X

L

X

X

↑

H

X

↑

L

↑ = Positive logic transition.

X = Don’t care.

Table I. Control-Logic Truth Table

Serial Shift Register Function

Shift-Register-Data Advanced One-Bit

Disables

No Effect

No Effect

Disabled

DAC Register Function

Latched

Updated with Current Shift Register Contents

Loaded with all Zeros

Latched with all Zeros

Previous SR Contents Loaded (Avoid usage of CLR

when LD is logic low, since SR data could be corrupted

if a clock edge takes place, while CLR returns high.)

Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format

MSB

B11 B10

B9

AD7390 D11 D10 D9

B8 B7

B6

B5 B4

B3

B2

B1

D8 D7

D6

D5 D4

D3

D2

D1

LSB

B0

D0

Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format

MSB

B9

B8

B7

B6

B5

B4

B3

B2

B1

AD7391 D9

D8

D7

D6

D5

D4

D3

D2

D1

LSB

B0

D0

REV. A

–5–

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