CY7C1339F-100BGC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1339F-100BGC Datasheet PDF : 17 Pages
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Pin Configurations (continued)
CY7C1339F
119-ball BGA
CY7C1339F (128K × 32)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
NC
NC
C
NC
A
A
VDD
A
A
NC
D
DQC
NC
VSS
NC
VSS
NC
DQB
E
DQC
DQC
VSS
CE1
VSS
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
DQC
DQC
BWc
ADV
BWB
DQB
DQB
H
DQC
DQC
VSS
GW
VSS
DQB
DQB
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
NC
BWA
DQA
DQA
M
VDDQ
DQD
VSS
BWE
VSS
DQA
VDDQ
N
DQD
DQD
VSS
A1
VSS
DQA
DQA
P
DQD
NC
VSS
A0
VSS
NC
DQA
R
NC
A
MODE VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
A0, A1, A
BWA,BWB
BWC,BWD
GW
BWE
CLK
CE1
CE2
BGA
P4,N4,
A2,C2,R2,
A3,B3,C3,
T3,T4,A5,
B5,C5,T5,
A6,C6,R6
L5,G5,G3,
L3
TQFP
37,36,
32,33,34,
35,44,45,
46,47,48,
49,50,81,
82,99,
100
93,94,95,
96
I/O
Input-
Synchronous
Description
Address Inputs used to select one of the 128K address locations.
Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
and CE1, CE2, and CE3 are sampled active. A1, A0 are fed to the two-bit
counter..
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
H4
88
Input-
Global Write Enable Input, active LOW. When asserted LOW on the
Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW[A:D] and BWE).
M4
87
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a byte write.
K4
89
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also
Clock
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
E4
98
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
B2
97
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE1 and CE3 to select/deselect the device.
Document #: 38-05217 Rev. *C
Page 3 of 17
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