CY7C1339G(2004) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1339G Datasheet PDF : 17 Pages
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Switching Waveforms
Read Cycle Timing[18]
tCYC
PRELIMINARY
CY7C1339G
CLK
ADSP
ADSC
ADDRESS
GW, BWE,
BW[A:D]
CE
ADV
OE
Data Out (Q)
tCH
t
CL
t
t
ADS ADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
A3
Burst continued with
new base address
tCES tCEH
Deselect
cycle
tADVS tADVH
ADV
suspends
burst.
High-Z
tCLZ
tCO
tOEHZ
Q(A1)
tOEV
tOELZ
tCO
tDOH
Q(A2)
Q(A2 + 1)
Single READ
Q(A2 + 2)
Q(A2 + 3)
BURST READ
tCHZ
Q(A2)
Q(A2 + 1)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Notes:
18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05520 Rev. *A
Page 11 of 17
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