CY7C1339G-200BGI 查看數據表（PDF） - Cypress Semiconductor
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CY7C1339G-200BGI Datasheet PDF : 18 Pages
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CY7C1339G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
3
4
A
VDDQ
A
B NC/288M CE2
C NC/144M A
A
ADSP
A
ADSC
A
VDD
D
DQC
NC
VSS
NC
E
DQC
DQC
VSS
CE1
F
VDDQ
DQC
VSS
OE
G
DQC
DQC
BWc
ADV
H
DQC
DQC
VSS
GW
J
VDDQ
VDD
NC
VDD
K
DQD
DQD
VSS
CLK
L
DQD
DQD
BWD
NC
M
VDDQ
DQD
VSS
BWE
N
DQD
DQD
VSS
A1
P
DQD
NC
VSS
A0
R
NC
A
MODE VDD
T
NC NC/72M A
A
U
VDDQ
NC
NC
NC
5
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
NC
6
7
A
VDDQ
NC/9M NC/576M
A
NC/1G
NC
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
NC
DQA
A
NC
NC/36M ZZ
NC
VDDQ
Pin Definitions
Name
A0, A1, A
BWA, BWB
BWC, BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
I/O
Description
Input-
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
are fed to the two-bit counter..
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is
loaded.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded. Not connected for BGA. Where referenced, CE3 is assumed active throughout this
document for BGA.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05520 Rev. *F
Page 3 of 18
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