CY7C1326F 查看數據表（PDF） - Cypress Semiconductor
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CY7C1326F Datasheet PDF : 15 Pages
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CY7C1326F
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle
Add. Used ZZ CE3 CE2 CE1
Unselected
None
L XX
H
Unselected
None
L HX
L
Unselected
None
L XL
L
Unselected
None
L HX
L
Unselected
None
L XL
L
Begin Read
External
L
LH
L
Begin Read
External
L
LH
L
Continue Read Next
L XX
X
Continue Read Next
L XX
X
Continue Read Next
L XX
H
Continue Read Next
L XX
H
Suspend Read Current
L XX
X
Suspend Read Current
L XX
X
Suspend Read Current
L XX
H
Suspend Read Current
L XX
H
Begin Write
Current
L XX
X
Begin Write
Current
L XX
H
Begin Write
External
L
LH
L
Continue Write Next
L XX
X
Continue Write Next
L XX
H
Suspend Write Current
L XX
X
Suspend Write Current
L XX
H
ZZ “Sleep”
None
H XX
X
ADSP
X
L
L
H
H
L
H
H
H
X
X
H
H
X
X
H
X
H
H
X
H
X
X
ADSC
L
X
X
L
L
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
ADV
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
X
H
H
H
H
X
OE
DQ
Write
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State X
Truth Table for Read/Write[2, 3]
Read
Function
GW
BWE
BWB
BWA
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
H
L
H
L
L
H
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE =L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA, BWB),BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05424 Rev. **
Page 6 of 15
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