CY7C1351-40 查看數據表（PDF） - Cypress Semiconductor
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CY7C1351-40 Datasheet PDF : 13 Pages
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Switching Waveforms (continued)
Burst Sequences
CY7C1351
CLK
tALS
tALH
ADV/LD
tCH tCL
tCYC
ADDRESS RA1
tAS tAH
WA2
RA3
WE
tWS tWH
BWS[3:0]
tWS tWH
tCES tCEH
CE
tCLZ
Data-
In/Out
tDOH
tCHZ
tDH
tCLZ
OQu11t a
Q1+1
Out
Q1+2 Q1+3
Out Out
D2
D2+1 D2+2 D2+3
Q3
In
In
In
In
Out
Device
tCDV
tCDV
tDS
originally deselected
The combination of WE & BWS[3:0] defines a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
Q3+1
Out
= DON’T CARE
= UNDEFINED
11
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