CY7C277 查看數據表（PDF） - Cypress Semiconductor
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CY7C277 Datasheet PDF : 13 Pages
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CY7C277
Functional Description
The CY7C277 is a high-performance 32K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package.
The ceramic package may be equipped with an erasure win-
dow; when exposed to UV light, the PROM is erased and can
then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current re-
quirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that the product will meet DC and AC
specification limits after customer programming.
On the 7C277, the outputs are pipelined through a mas-
ter-slave register. On the rising edge of CP, data is loaded into
the 8-bit edge triggered output register. The E/ES input pro-
vides a programmable bit to select between asynchronous
and synchronous operation. The default condition is asynchro-
nous. When the asynchronous mode is selected, the E/ES pin
operates as an asynchronous output enable. If the synchro-
nous mode is selected, the E/ES pin is sampled on the rising
edge of CP to enable and disable the outputs. The 7C277 also
provides a programmable bit to enable the Address Latch in-
put. If this bit is not programmed, the device will ignore the ALE
pin and the address will enter the device asynchronously. If the
ALE function is selected, the address enters the PROM while
the ALE pin is active, and is captured when ALE is deasserted.
The user may define the polarity of the ALE signal, with the
default being active HIGH.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................−65°C to +150°C
Ambient Temperature with
Power Applied.................................................−55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage ................................................. −3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm2
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Ambient Temperature
Commercial
Industrial[1]
Military[2]
0°C to +70°C
−40°C to +85°C
−55°C to +125°C
VCC
5V ±10%
5V ±10%
5V ±10%
Electrical Characteristics Over the Operating Range[3, 4]
7C277-30 7C277-40, 50
Parameter
Description
Test Conditions
Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Level
VCC = Min., IOH = − 2.0 mA
VCC = Min., IOL = 8.0 mA
Guaranteed Input Logical HIGH
Voltage for All Inputs
2.4
2.4
V
0.4
0.4
V
2.0 VCC 2.0 VCC
V
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
0.8
0.8
V
IIX
Input Leakage Current
GND < VIN < VCC
−10 +10 −10 +10 µA
VCD
Input Clamp Diode Voltage
Note 4
IOZ
Output Leakage Current
0 < VOUT < VCC, Output Disabled[5] −40 +40 −40 +40 µA
IOS
Output Short Circuit Current
VCC = Max., VOUT = 0.0V[6]
−20 −90 −20 −90 mA
ICC
Power Supply Current
VCC = Max., CS > VIH Commercial
120
IOUT = 0 mA
Military
120 mA
130
VPP
Programming Supply Voltage
12 13 12
13
V
IPP
Programming Supply Current
50
50 mA
VIHP
Input HIGH Programming Voltage
3.0
3.0
V
VILP
Input LOW Programming Voltage
0.4
0.4
V
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04006 Rev. **
Page 2 of 13
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