CY7C43682-7AC 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
比赛名单
CY7C43682-7AC Datasheet PDF : 30 Pages
| |||
CY7C43642
CY7C43662
CY7C43682
Functional Description
The CY7C436X2 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, RST1 and RST2.
The CY7C436X2 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First-Word Fall-Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state.”[2]
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB are loaded
in parallel using Port A. Three default offset settings are also
provided. The AEA and AEB threshold can be set at 8, 16, or
64 locations from the empty boundary and AFA and AFB
threshold can be set at 8, 16, or 64 locations from the full
boundary. All these choices are made using the FS0 and FS1
inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X2 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
CY7C43642/62/82
-7
133
6
7.5
3
0
6
100
CY7C43642/62/82
-10
100
8
10
4
0
8
100
CY7C43642/62/82
-15
66.7
10
15
5
0
8
100
100
CY7C43642
CY7C43662
CY7C43682
Density
1K x 36
4K x 36
16K x 36
Package
120 TQFP
120 TQFP
120 TQFP
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06019 Rev. *B
Page 3 of 30
Share Link: 