CY7C43682AV-7AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43682AV-7AC Datasheet PDF : 30 Pages
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CY7C43642AV
CY7C43662AV
CY7C43682AV
AC Test Loads and Waveforms (–10 and –15)
3.3V
R1 = 330Ω
OUTPUT
[17]
CL = 30 pF
R2 = 680Ω
INCLUDING
JIG AND
SCOPE
AC Test Loads and Waveforms (–7)
VCC/2
50 Ω
I/O
Z0 = 50Ω
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Switching Characteristics Over the Operating Range
Parameter
Description
fS
tCLK
tCLKH
tCLKL
tDS
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A0–35 before CLKA↑ and B0–35 before
CLKB↑
tENS
Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA↑;
CSB, W/RB, ENB, and MBB before CLKB↑
tRSTS
Set-Up Time, MRST1, MRST2, RT1 or RT2 LOW before
CLKA↑ or CLKB↑[17]
tFSS
Set-Up Time, FS0 and FS1 before MRST1 and MRST2
HIGH
tFWS
tDH
tENH
Set-Up Time, FWFT before CLKA↑
Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
tRSTH
Hold Time, MRST1, MRST2, RT1 or RT2 LOW after
CLKA↑ or CLKB↑[17]
Notes:
17. CL = 5 pF for tDIS.
18. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
CY7C43642/
62/82AV
–7
Min. Max.
133
7.5
3.5
3.5
3
3
2.5
5
0
0
0
1
CY7C43642/
62/82AV
–10
Min. Max.
100
10
4
4
4
4
4
7
0
0
0
2
CY7C43642/
62/82AV
–15
Min. Max.
67
15
6
6
5
5
5
7.5
0
0
0
2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-06020 Rev. *C
Page 11 of 30
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