CY7C43682AV-15AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43682AV-15AC Datasheet PDF : 30 Pages
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CY7C43642AV
CY7C43662AV
CY7C43682AV
Signal Description
Reset (MRST1, MRST2)
Each of the two FIFO memories of the CY7C436X2AV
undergoes a complete reset by taking its associated Master
Reset (MRST1, MRST2) input LOW for at least four Port A
clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH
transitions. The Master Reset inputs can switch asynchro-
nously to the clocks. A Master Reset initializes the internal
Read and Write pointers and forces the Full/Input Ready flag
(FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag
(EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA,
AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A
Master Reset also forces the Mailbox flag (MBF1, MBF2) of
the parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two clock cycles
to begin normal operation. A Master Reset must be performed
on the FIFO after power up, before data is written to its
memory.
A LOW-to-HIGH transition on a FIFO reset (MRST1, MRST2)
input latches the values of the Flag select (FS0, FS1) for
choosing the Almost Full and Almost Empty offset
programming method (see Almost Empty and Almost Full flag
offset programming below).
First-Word Fall-Through (FWFT/STAN)
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) mode.
Once the Master Reset (MRST1, MRST2) input is HIGH, a
HIGH on the FWFT/STAN input at the second LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
CY Standard mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
Read from the FIFO, including the first, must be requested
using a formal Read operation.
Once the Master Reset (MRST1, MRST2) input is HIGH, a
LOW on the FWFT/STAN input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A0–35 or B0–35). It also uses the Input Ready
function (IRA, IRB) to indicate whether or not the FIFO
memory has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to data
outputs, no Read request necessary. Subsequent words must
be accessed by performing a formal Read operation.
Following Master Reset, the level applied to the FWFT/STAN
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2AV are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs.
To program the X1, X2, Y1, and Y2 registers in parallel from
Port A, perform a Master Reset on both FIFOs simultaneously
with SPM HIGH and FS0 and FS1 LOW during the
LOW-to-HIGH transition of MRST1 and MRST2. After this
reset is complete, the first four Writes to FIFO1 do not store
data in RAM but load the offset registers in the order Y1, X1,
Y2, X2. The Port A data inputs used by the offset registers are
(A0–9), (A0–11), or (A0–13), for the CY7C436X2AV, respectively.
The highest numbered input is used as the most significant bit
of the binary number in each case. Valid programming values
for the registers range from 0 to 1023 for the CY7C43642AV;
0 to 4095 for the CY7C43662AV; 0 to 16383 for the
CY7C43682AV.[1] After all the offset registers are
programmed from Port A, the Port B Full/Input Ready
(FFB/IRB) is set HIGH and both FIFOs begin normal
operation.
FS0 and FS1 function the same way in both CY Standard and
FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO Reads and Writes on Port A are independent of any
concurrent Port B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read select (W/RB). The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs when CSB
is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data
is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3).
FIFO Reads and Writes on Port B are independent of any
concurrent Port A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read selects are only for enabling
Write and Read operations and are not related to
high-impedance control of the data outputs. If a port enable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read select may change states during the set-up and
hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
Document #: 38-06020 Rev. *C
Page 6 of 30
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