CY7C43683 查看數據表（PDF） - Cypress Semiconductor
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CY7C43683 Datasheet PDF : 29 Pages
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CY7C43643
CY7C43663
CY7C43683
Pin Definitions
Signal Name Description I/O
Function
A0–35
AE
Port A Data
Almost Empty
Flag (Port B)
I 36-bit unidirectional data port for side A.
O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
number of words in the FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X.[1]
AF
Almost Full Flag O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in the FIFO is less than or equal to the value in the Almost Full A
offset register, Y.[1]
B0–35
BE/FWFT
Port B Data
O 36-bit unidirectional data port for side B.
Big
I This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
Endian/First-Wor
operation. In this case, depending on the bus size, the most significant byte or word on
d Fall-Through
Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In
Select
this case, the least significant byte or word on Port A is transferred to Port B first. After
Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard
Mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been
selected, the level on FWFT must be static throughout device operation.
BM
Bus Match
I A HIGH on this pin enables either byte or word bus width on Port B, depending on
Select (Port B)
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA
Port A Clock
I CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA
CSB
EF/OR
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR
reading. EF/OR
indicates the presence
is synchronized to the
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for
ENA
Port A Enable
I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write
data on Port A.
ENB
Port B Enable
I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write
data on Port B.
FF/IR
Port B Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary
flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06021 Rev. *B
Page 3 of 29
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