CY7C43683-15AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43683-15AC Datasheet PDF : 29 Pages
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CY7C43643
CY7C43663
CY7C43683
Pin Definitions (continued)
Signal Name Description
FS1/SEN
Flag Offset
Select 1/Serial
Enable
FS0/SD
Flag Offset
Select 0/Serial
Data
MBA
MBB
Port A Mailbox
Select
Port B Mailbox
Select
MBF1
MBF2
MRS1
Mail1 Register
Flag
Mail2 Register
Flag
Master Reset
MRS2
PRS
Master Reset
Partial Reset
RT
SIZE
Retransmit
Bus Size Select
SPM
W/RA
W/RB
Serial
Programming
Port A
Write/Read
Select
Port B
Write/Read
Select
I/O
Function
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
I
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 20 for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first
bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When a read operation is performed on Port B, a HIGH level on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO output register data for output.
Data can only be written into Mail 2 register through Port B (MBB HIGH) and not into
the FIFO memory.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
I A LOW on this pin initializes the Mail2 register.
I A LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
I A LOW strobe on this pin will retransmit data on the FIFO. This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operation to retransmit the data. Retransmit function applies to CY standard mode only.
I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must be
static throughout device operation.
I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
I A HIGH selects a write operation and a LOW selects a read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
state when W/RB is LOW.
Document #: 38-06021 Rev. *B
Page 4 of 29
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