CY7C43684AV-10AC 查看數據表（PDF） - Cypress Semiconductor

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CY7C43684AV-10AC

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644AV

CY7C43664AV

CY7C43684AV

employs data lines A0<17. (In this case, A18<35 are “Don’t

Care” inputs.) If the selected Port A bus size is 9 bits, then the

usable width of the Mail1 Register employs data lines A0<8. (In

this case, A9<35 are “Don’t Care” inputs.)

A LOW-to-HIGH transition on CLKB writes B0<35 data to the

Mail2 Register when a Port B Write is selected by CSB LOW,

W/RB LOW, ENB HIGH and MBB HIGH. If the selected Port B

bus size is also 36 bits, then the usable width of the Mail2

Register employs data lines B0–35. If the selected Port B bus

size is 18 bits, then the usable width of the Mail2 Register

employs data lines B0–17. (In this case, B18–35 are “Don’t Care”

inputs.) If the selected Port B bus size is 9 bits, then the usable

width of the Mail2 Register employs data lines B0<8. (In this

case, B9<35 are “Don’t Care” inputs.)

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Any Attempt to write to a mail register

are ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox

Select input is LOW and from the mail register when the port

Mailbox Select input is HIGH.

The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-

HIGH transition on CLKB when a Port B Read is selected by

CSB LOW, W/RB HIGH, ENB HIGH AND MBB HIGH. For a

36-bit bus size, 36 bits of mailbox data are placed on B0–35.

For an 18-bit bus size, 18 bits of mailbox data are placed on

B0–17. (In this case, B18–35 are indeterminate.) For a 9-bit bus

size, 9 bits of mailbox data are placed on B0–8. (In this case,

B9–35 are indeterminate.)

The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-

HIGH transition on CLKA when a Port A Read is selected by

CSA LOW, W/RA LOW, ENA HIGH, MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on

A0–35. For an 18-bit bus size, 18 bits of mailbox data are

placed on A0–17. (In this case, A18–35 are indeterminate.) For

a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In

this case, A9–35 are indeterminate.)

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Select feature has no effect on the mailbox data.

Bus Sizing

The Port B bus can be configured in a 36-bit long-word, 18-bit

word, or 9-bit byte format for data read from FIFO1 or written

to FIFO2. The levels applied to the Port B Bus Size Select

(SIZE) and the Bus Match Select (BM) determine the Port B

bus size. These levels should be static throughout FIFO

operation. Both bus size selections are implemented at the

completion of Master Reset, by the time the Full/Input Ready

flag is set HIGH.

Two different methods for sequencing data transfer are

available for Port B when the bus size selection is either byte-

or word-size. They are referred to as Big Endian (most signif-

icant byte first) and Little Endian (least significant byte first).

The level applied to the Big Endian Select (BE) input during

the LOW-to-HIGH transition of MRS1 and MRS2 selects the

endian method that will be active during FIFO operation. BE is

a “Don’t Care” input when the bus size selected for Port B is

long word. The endian method is implemented at the

completion of Master Reset, by the time the Full/Input Ready

flag is set HIGH.

Bus-Matching operations are not available when transferring

data via mailbox registers. Furthermore, both the word- and

byte-size bus selections limit the width of the data bus that can

be used for mail register operations. In this case, only those

byte lanes belonging to the selected word- or byte-size bus

can carry mailbox data. The remaining data outputs will be

indeterminate. The remaining data inputs will be don’t care

inputs. For example, when a word-size bus is selected, then

mailbox data can be transmitted only between A0–17 and

B0–17. When a byte-size bus is selected, then mailbox data

can be transmitted only between A0–8 and B0–8.

Bus-Matching FIFO1 Reads

Data is read from the FIFO1 RAM in 36-bit long-word incre-

ments. If a long-word bus size is implemented, the entire long-

word immediately shifts to the FIFO1 output register. If byte or

word size is implemented on Port B, only the first one or two

bytes appear on the selected portion of the FIFO1 output

register, with the rest of the long-word stored in auxiliary

registers. In this case, subsequent FIFO1 reads output the rest

of the long word to the FIFO1 output register.

When reading data from FIFO1 in the byte or word format, the

unused B0–35 outputs are indeterminate.

Bus-Matching FIFO2 Writes

Data is written to the FIFO2 RAM in 36-bit long-word incre-

ments. Data written to FIFO2 with a byte or word bus size

stores the initial bytes or words in auxiliary registers. The

CLKB rising edge that writes the fourth byte or the second

word of long-word to FIFO2 also stores the entire long word in

FIFO2 RAM.

Reading from FIFO2 on Port A can only be in 36-bit format

Retransmit (RT1, RT2)

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. The retransmit

function applies to CY Standard mode only.

The number of 36-/18-/9-bit words written into the FIFO should

be less than full depth minus 2/4/8 words between the reset of

the FIFO (master or partial) and Retransmit setup. A LOW

pulse on RT1, (RT2) resets the internal Read pointer to the first

physical location of the FIFO. CLKA and CLKB may be free

running but ENB (ENA) must be disabled during and tRTR after

the retransmit pulse. With every valid Read cycle after retrans-

mit, previously accessed data is read and the Read pointer is

incremented until it is equal to the Write pointer. Flags are

governed by the relative locations of the Read and Write point-

ers and are updated during a retransmit cycle. Data written to

the FIFO after activation of RT1, (RT2) are transmitted also.

The full depth of the FIFO can be repeatedly retransmitted.

Document #: 38-06025 Rev. *C

Page 10 of 37

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