CY7C43684AV 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

比赛名单

CY7C43684AV

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644AV

CY7C43664AV

CY7C43684AV

Pin Definitions (continued)

Signal Name Description I/O

Function

MRS2

FIFO2 Master

Reset

I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location

of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2

selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH

transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2

is LOW.

PRS1

FIFO1 Partial

Reset

I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location

of memory and sets the Port B output register to all zeroes. During Partial Reset, the

currently selected bus size, endian arrangement, programming method (serial or

parallel), and programmable flag settings are all retained.

PRS2

FIFO2 Partial

Reset

I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location

of memory and sets the Port A output register to all zeroes. During Partial Reset, the

currently selected bus size, endian arrangement, programming method (serial or

parallel), and programmable flag settings are all retained.

RT1

Retransmit

I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by

FIFO1

bringing the Read pointer back to location zero. The user will still need to perform Read

operations to retransmit the data. Retransmit function applies to CY standard mode

only.

RT2

Retransmit

I A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by

FIFO2

bringing the Read pointer back to location zero. The user will still need to perform Read

operations to retransmit the data. Retransmit function applies to CY standard mode

only.

SIZE

Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A

LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM

and BE to select the bus size and endian arrangement for Port B. The level of SIZE

must be static throughout device operation.

SPM

Serial

Programming

I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on

this pin selects parallel programming or default offsets (8, 16, or 64).

W/RA

Port A Write/

Read Select

I A HIGH selects a Write operation and a LOW selects a Read operation on Port A

for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance

state when W/RA is HIGH.

W/RB

Port B Write/

Read Select

I A LOW selects a Write operation and a HIGH selects a Read operation on Port B

for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance

state when W/RB is LOW.

Document #: 38-06025 Rev. *C

Page 6 of 37

Share Link: