DG406DN-E3 查看數據表（PDF） - Vishay Semiconductors
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DG406DN-E3 Datasheet PDF : 14 Pages
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www.vishay.com
SCHEMATIC DIAGRAM (Typical Channel)
DG406, DG407
Vishay Siliconix
V+
GND
VREF
A0
AX
V+
EN
Level
Shift
Decode/
Drive
V-
TEST CIRCUITS
Fig. 1
+ 15 V
+ 2.4 V
V+
EN
S1
A3
A2
S2 - S 15
DG406
A1
S16
A0
D
GND V-
50 Ω
300 Ω
- 15 V
± 10 V
± 10 V
VO
35 pF
+ 15 V
+ 2.4 V
EN
V+
S1b
± 10 V
A2 DG407
*
A1
S8b
A0
Db
GND V-
50 Ω
300 Ω
- 15 V
± 10 V
VO
35 pF
Logic 3 V
Input
0V
VS1
Switch
Output
VO
0V
VS8
tTRANS
S1 ON
* = S1a - S8a, S2b S ± 7b, Da
Fig. 2 - Transition Time
D
V+
V-
S1
Sn
50 %
tr < 20 ns
tf < 20 ns
90 %
S8 ON
90 %
tTRANS
S13-2518-Rev. K, 09-Dec-13
8
Document Number: 70061
For technical questions, contact: analogswitchsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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