DM96L02 查看數據表（PDF） - Fairchild Semiconductor
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DM96L02 Datasheet PDF : 6 Pages
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Functional Block Diagram
Operation Notes
1. TRIGGERING—can be accomplished by a positive-
going transition on pin 4 (12) or a negative-going transi-
tion on pin 5 (11). Triggering begins as a signal crosses
the input VIL:VIH threshold region; this activates an
internal latch whose unbalanced cross-coupling causes
it to assume a preferred state. As the latch output goes
LOW it disables the gates leading to the Q output and,
through an inverter, turns on the capacitor discharge
transistor. The inverted signal is also fed back to the
latch input to change its state and effectively end the
triggering action; thus the latch and its associated feed-
back perform the function of a differentiator.
The emitters of the latch transistors return to ground
through an enabling transistor which must be turned off
between successive triggers in order for the latch to
proceed through the proper sequence when triggering
is desired. Pin 5 (11) must be HIGH in order to trigger
at pin 4 (12); conversely, pin 4 (12) must be LOW in
order to trigger at pin 5 (11).
2. RETRIGGERING—In a normal cycle, triggering ini-
tiates a rapid discharge of the external timing capacitor,
followed by a ramp voltage run-up at pin 2 (14). The
delay will time out when the ramp voltage reaches the
upper trigger point of a Schmitt circuit, causing the out-
puts to revert to the quiescent state. If another trigger
occurs before the ramp voltage reaches the Schmitt
threshold, the capacitor will be discharged and the
ramp will start again without having disturbed the out-
put. The delay period can therefore be extended for an
arbitrary length of time by insuring that the interval
between triggers is less than the delay time, as deter-
mined by the external capacitor and resistor.
3. NON-RETRIGGERABLE OPERATION—Retriggering
can be inhibited logically, by connecting pin 6 (10) back
to pin 4 (12) or by connecting pin 7 (9) back to pin 5
(11). Either hook-up has the effect of keeping the latch-
enabling transistor turned on during the delay period,
which prevents the input latch from cycling as dis-
cussed above in the section on triggering.
4. OUTPUT PULSE WIDTH—An external resistor RX and
an external capacitor CX are required, as shown in the
functional block diagram. To minimize stray capaci-
tance and noise pickup, RX and CX should be located
as close as possible to the circuit. In applications which
require remote trimming of the pulse width, as with a
variable resistor, RX should consist of a fixed resistor in
series with the variable resistor; the fixed resistor
should be located as close as possible to the circuit.
The output pulse width tW is defined as follows, where
RX is in kΩ, CX is in pF and tW is in ns.
tW = 0.33 RXCX (1 + 3/RX) for CX ≥ 103 pF
16 kΩ ≤ RX ≤ 220 kΩ for 0°C to +75°C
20 kΩ ≤ RX ≤ 100 kΩ for −55°C to +125°C
CX may vary from 0 to any value. For pulse widths with
CX less than 103 pF see Figure 1.
5. SETUP AND RELEASE TIMES—The setup times
listed below are necessary to allow the latch-enabling
transistor to turn off and the node voltages within the
input latch to stabilize, thus insuring proper cycling of
the latch when the next trigger occurs. The indicated
release times (equivalent to trigger duration) allow time
for the input latch to cycle and its signal to propagate.
6. RESET OPERATION—A LOW signal on CD, pin 3
(13), will terminate an output pulse, causing Q to go
LOW and Q to go HIGH. As long as CD is held LOW, a
delay period cannot be initiated nor will attempted trig-
gering cause spikes at the outputs. A reset pulse dura-
tion, in the LOW state, of 25 ns is sufficient to insure
resetting. If the reset input goes LOW at the same time
that a trigger transition occurs, the reset will dominate
and the outputs will not respond to the trigger. If the
reset input goes HIGH coincident with a trigger transi-
tion, the circuit will respond to the trigger.
Input to Pin 5 (11)
Pin 4 (12) = L
Pin 3 (13) = H
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Input to Pin 4 (12)
Pins 5 (11) and 3 (13) = H
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