DM9102H 查看數據表（PDF） - Davicom Semiconductor, Inc.

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产品描述 (功能)

比赛名单

DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

7

0

6

0

5

0

4

0

3

0

2

1

1

1

0

1

DM9102H

Single Chip Fast Ethernet NIC Controller

will be asserted on detection of an address parity error and if both this bit

and bit 6 are set

RO

Address/Data Stepping (0 for No Stepping)

RW

Parity Error Response Enable/Disable

Setting this bit will enable the DM9102H to assert PERR# on the detection

of a data parity error and to assert SERR# for reporting address parity

error

RO

VGA Palette Snooping (0 for No Support)

RO

Memory Write and Invalid (0 for No Implementation)

The DM9102H only generates memory write cycle

RO

Special Cycles (0 for No Implementation)

RW

Master Device Capability Enable/Disable

When this bit is set, DM9102H has the ability of master mode operation

RW

Memory Space Access Enable/Disable

This bit controls the ability of memory space access. The memory access

includes memory mapped I/O access and Boot ROM access. As the

system boots up, this bit will be enabled by BIOS for Boot ROM memory

access. While in normal operation, using memory mapped I/O access,

this bit should be set by driver before memory access cycles

RW

I/O Space Access Enable/Disable

This bit controls the ability of I/O space access. It will be set by BIOS after

power on

6.1.3 Revision ID (xxxxxx08H - PCIRV)

31

Class Code

Revision Major Number

Revision Minor Number

Class Code

87

43

0

Revision ID

Bit

Default

31:8 020000H

7:4

0110

3:0

0000

Type

RO

RO

RO

Description

Class Code (020000H)

This is the standard code for Ethernet LAN controller

Revision Major Number

This is the silicon-major revision number that will increase for the subsequent

versions of the DM9102H

Revision Minor Number

This is the silicon-minor revision number that will increase for the subsequent

versions of the DM9102H

Final

11

Version: DM9102H-12-DS-F01

February 15, 2008

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