DS2167/DS2168
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE
DESCRIPTION
1
RST
I Reset. A high-low-high transition clears all internal registers and reset both algo-
rithms. The device should be reset on system power-up, and/or when changing
to/from hardware mode.
2
TM0
3
TM1
I Test Modes 0 and 1. Tie to VSS for normal operation
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
I Address Select. A0=LSB; A5=MSB. Must match address/command word to en-
able serial port write.
10
SPS
I Serial Port Select. Tie to VDD to select the serial port, to VSS to select the hard-
ware mode.
11 MCLK
I Master Clock. 10 MHz clock for ADPCM processing “engine”; may asynchronous
to SCLK, CLKX and CLKY.
12
VSS
– Signal Ground. 0.0 volts
13
XIN
I X Data In. Samples on falling edge of CLKX during selected timeslots.
14 CLKX
I X Data Clock. Data clock for X side PCM interface; must be coherent and rising
edge aligned with FSX.
15
FSX
I X Frame Sync. 8 KHz frame sync for X side PCM interface.
16 XOUT
O X Data Out. Updated on rising edge of CLKX during selected timeslots.
17 SCLK
I Serial Data Clock. Used to write serial port registers.
18
SDI
I Serial Data In. Data for onboard control registers. Sampled on rising edge of
SCLK.
19
CS
I Chip Select. Must be low to write the serial port.
20 YOUT
O Y Data Out. Updated on rising edge of CLKY during selected timeslots.
21
FSY
I Y Frame Sync. 8 KHz frame sync for Y side PCM interface.
22 CLKY
I Y Data Clock. Data clock for Y side PCM interface; must be coherent and rising
edge aligned with FSY.
23
YIN
I Y Data In. Samples on falling edge of CLKY during selected timeslots.
24
VDD
– Positive Supply. 5.0 volts.
HARDWARE RESET
RST allows the user to reset both channel algorithms
and register contents. This input must be held low for at
least 1 ms on system power-up after master clock is
stable to assure proper initialization of the device. RST
should also be asserted when changing to/from the
hardware mode. RST clears all bits of the control regis-
ter except IPD; IPD is set for both channels, powering
down the device.
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