DS2149 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

比赛名单

DS2149

5V T1/J1 Line Interface Unit

Maxim Integrated 

DS2149

Table 2-C. Signal Descriptions

PIN NAME

1

MCLK

2

TCLK

TPOS

3

TDATA

INSLER

TNEG

4

INSBPV

5

MODE1

RNEG

6

BPV

RPOS

7

RDATA

8

RCLK

9

MODE0

10

VSM

11

JASEL

RCL

12

QPD

13/

TTIP/

16 TRING

14

VSS

15

TVDD

I/O

FUNCTION

I

Master Clock. A 1.544MHz clock source with TTL levels is applied at this pin. This

clock is used internally for both clock/data recovery and for jitter attenuation.1

I

Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit

side formatter. Can be sourced internally by MCLK or RCLK.

Transmit Positive Data. Sampled on the falling edge of TCLK for data to be

transmitted out onto the line.

Transmit NRZ Data. Sampled on the falling edge of TCLK for data to be transmitted

I onto the line.

Transmit Insert Logic Error. Rising edge on INSLER inserts a logic error into the

outbound QRSS pattern. Sampled on falling edge of TCLK.

Transmit Negative Data. Sampled on the falling edge of TCLK for data to be

I

transmitted out onto the line.

Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK.

Rising edge inserts one BPV.

I2

Mode Select 1. Connect low to select hardware mode. Connect high to select serial

port mode. See also MODE0.

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

(CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Always valid

O on rising edge of RCLK in hardware mode.

Receive Bipolar Violation. Transitions high for one clock cycle marking an inbound

bipolar violation. Valid on rising edge of RCLK.

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

(CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Always valid on

rising edge of RCLK in hardware mode.

O Receive Data. RDATA is the NRZ output from the line interface. Set NRZE

(CCR1.6) to a 1 for NRZ applications. In NRZ mode, data is output on RPOS while a

received error causes a positive-going pulse synchronous with RCLK at RNEG

(Section 6).

O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in

absence of signal at RTIP and RRING.

I2

Mode Select 0. Set high to disable all output pins (including the serial control port).

Set low for normal operation. Useful in board level testing. See also MODE1.

I Voltage Supply Mode. Connect high for 5V operation. Has 10kW pullup.

Jitter Attenuator Select

0 = Place the jitter attenuator on the transmit side

I2 1 = Place the jitter attenuator on the receive side

Float = Disable jitter attenuator

Not used in software mode

Receive Carrier Loss. An output that toggles high during a receive carrier loss.

O QPD. Output high when QRSS detector is searching for QRSS data pattern. Output

high for one-half clock cycle on bit error. Connect to external counter to count bit

errors.

O

Transmit Tip and Ring. Analog line driver outputs. These pins connect through a

step-up transformer to the line (Section 5).

— Ground for Transmitter Block

— Positive Supply. 5.0V ±5% for the transmitter block. See also VSM pin 10.

7 of 32

Share Link: