EL4511 查看數據表（PDF） - Intersil
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EL4511 Datasheet PDF : 24 Pages
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EL4511
TABLE 3. MODE CONTROL TRUTH TABLE
(see also Table 2 for hardware over-ride)
MODE EnTri EnBi EnHin TriLevel Hin HinVin
CTRL Level Level Vin Priority Priority Only
Reg 1
b5 b4 b3
000 1
1
1
0
0
0
001 1
1
1
0
1
0
010 1
1
1
1
0
0
011 1
0
0
1
0
0
100 0
1
1
0
0
0
101 0
1
0
0
0
0
110 0
1
1
0
1
0
111 0
1
1
0
1
1
EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync
detection, two-level sync detection and separate H/V (VGA) sync
detection, respectively.
Other signals used to prioritize tri-level syncs (TriLevPriority),
separate H/V (Hin Priority), or to only allow signals from
HIN/VERTIN (HinVinOnly).
TABLE 4. ACQUISITION CONTROL SIGNALS
REGISTER BIT
SIGNAL
NAME
DESCRIPTION
8
3 En50Slice 1 = Sample and Hold front
end is in use
8
1 Progressive 1 = Progressive scan
detected
8
0 Tri-Level
1 = Tri-Level syncs detected
Detected
9
5 ENLEVEL 1 = VLEVEL is available
BLANKING when system is not locked
9
4 ENLEVEL 1 = Disable VLEVEL Output
9
2 ENALOS 1 = Analog loss of signal not
used in lock indication.
14
5 SYNCLOCK Same information as
SYNCLOCK pin 3
16
4 RateLocked Line rate is locked
16
3 ALOS
Sync Amplitude is below
minimum
21
FN7009.7
July 21, 2005
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