EM6A9320 查看數據表（PDF） - Etron Technology

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EM6A9320

4M x 32 DDR SDRAM

Etron Technology 

Et r onT ec h

4Mx32 DDR SDRAM

EM6A9320

Decoupling Capacitance Guide Line

Symbol

Parameter

CDC1 Decouping Capacitance between VDD and VSS

CDC2 Decouping Capacitance between VDDQ and VSSQ

Value

Unit

0.1+0.01

uF

0.1+0.01

uF

AC Input Operating Conditions

(VDD = 2.8V ± 5% for 350, 333, 300, or 285MHz, VDD=2.5 ± 5% for 250 or 200MHz, TA = 0~70 °C)

Symbol

Parameter

Min

Max

VIH Input High Voltage; DQ

VREF+0.4

-

VIL Input Low Voltage; DQ

-

VREF-0.4

VID Clock Input Differential Voltage; Ck & CK#

0.8

VDDQ+0.6

VIX Clock Input Crossing Point Voltage; Ck & CK# 0.5xVDDQ-0.2 0.5xVDDQ+0.2

Unit

V

V

V

V

Note

AC Operating Test Conditions

(VDD = 2.8V ± 5% for 350, 333, 300, or 285MHz, VDD=2.5 ± 5% for 250 or 200MHz, TA = 0~70 °C)

Reference Level of Output Signals (VRFE)

0.5 x VDDQ

CK & CK# signal maximum peak swing

1.5V

Output Load

See Figure. A Test Load

Input Signal Levels

VREF+0.4 V / VREF-0.4 V

Input Signals Slew Rate

1 V/ns

Input timing measurement reference level

VREF

Output timing measurement reference level

VTT

Reference Level of Input Signals

0.5 x VDDQ

Figure A. Test Load

DQ,DQS

VΤΤ=0.5 x V∆∆Θ

:

Z0=50 W

30pF VREF=0.5 x VDDQ

Etron Confidential

10

Rev 0.3

July. 2002

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