AD7304BRZ1 查看數據表（PDF） - Analog Devices
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AD7304BRZ1 Datasheet PDF : 20 Pages
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AD7304/AD7305
Table 6. AD7305 Control Logic Truth Table
WR 1 A1 A0 LDAC2 Input Register Function
L
LLH
Register A loaded with DB0 to DB7
↑+ L L H
Register A latched with DB0 to DB7
L
L HH
Register B loaded with DB0 to DB7
↑+ L H H
Register B latched with DB0 to DB7
L
HL H
Register C loaded with DB0 to DB7
↑+ H L H
Register C latched with DB0 to DB7
L
HHH
Register D loaded with DB0 to DB7
↑+ H H H
Register D latched with DB0 to DB7
H
XXL
No effect
L
XXL
Input register x transparent to DB0 to DB7
H
X X ↑+
No effect
H
XXH
No effect, device not selected
DAC Register Function
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
All input register contents loaded, register transparent
Register transparent
All input register contents latched
No effect, device not selected
1 ↑+ positive logic transition; ↓– negative logic transition; X don’t care.
2 LDAC is a level-sensitive input.
WR
A0, A1
D0–D7
LDAC
VOUT
tWR
tAS
tAH
tDS
tDH
tLS
tLH
tS
tLDW
±1 LSB
ERROR BAND
Figure 6. AD7305 General Timing Diagram
A0/SHDN
IDD
tSDN
tSDR
Figure 7. AD7305 Timing Diagram Zoom In
Rev. C | Page 7 of 20
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