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MC74F568 查看數據表(PDF) - Motorola => Freescale

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MC74F568 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
4-BIT BIDIRECTIONAL COUNTERS
(WITH 3-STATE OUTPUTS)
The MC54/ 74F568 and MC54/74F569 are fully synchronous, reversible
counters with 3-state outputs. The F568 is a BCD decade counter; the F569
is a binary counter. They feature preset capability for programmable opera-
tion, carry lookahead for easy cascading, and a U/D input to control the direc-
tion of counting. For maximum flexibility there are both synchronous and mas-
ter asynchronous reset inputs as well as both Clocked Carry (CC) and
Terminal Count (TC) outputs. All state changes except Master Reset are initi-
ated by the rising edge of the clock. A HIGH signal on the Output Enable (OE)
input forces the output buffers into the high impedance state but does not pre-
vent counting, resetting or parallel loading.
4-Bit Bidirectional Counting
F568 Decade Counter
F569 Binary Counter
Synchronous Counting and Loading
Lookahead Carry Capability for Easy Cascading
Preset Capability for Programmable Operation
3-State Outputs for Bus Organized Systems
Master Reset (MR) Overrides All Other Inputs
Synchronous Reset (SR) Overrides Counting and Parallel Loading
CONNECTION DIAGRAM
VCC TC CC OE O0 O1 O2 O3 CET PE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
U/D CP P0 P1 P2 P3 CEP MR SR GND
MC54/74F568
MC54/74F569
4-BIT
BIDIRECTIONAL
COUNTERS
(WITH 3-STATE OUTPUTS)
FASTSCHOTTKY TTL
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
MC54FXXXJ Ceramic
MC74FXXXN Plastic
MC74FXXXDW SOIC
LOGIC SYMBOL
11 3 4 5 6
PE P0 P1 P2 P3
1
U/D
7
CEP
12
CET
2
CP
CC
18
TC
19
17
OE
MR SR O0 O1 O2 O3
8 9 16 15 14 13
FAST AND LS TTL DATA
4-220

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