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FSL116LR 查看數據表(PDF) - Fairchild Semiconductor

零件编号
产品描述 (功能)
比赛名单
FSL116LR
Fairchild
Fairchild Semiconductor Fairchild
FSL116LR Datasheet PDF : 13 Pages
First Prev 11 12 13
Physical Dimensions
9.83
9.00
6.67
6.096
5.08 MAX
3.683
3.20
8.255
7.61
7.62
0.33 MIN
(0.56)
2.54
3.60
3.00
0.56
0.355
1.65
1.27
7.62
0.356
0.20
9.957
7.87
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 24. 8-Lead, Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FSL116LR • Rev. 1.0.1
12
www.fairchildsemi.com

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