GS1582(2007) 查看數據表（PDF） - Gennum -> Semtech

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GS1582
(Rev.:2007)

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

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GS1582 Data Sheet

Table 1-1: Pin Descriptions (Continued)

Pin

Number

Name

Timing

Type Description

K4

AIN_7/8

Synchronous Input Serial Audio Input; Channels 7 and 8.

with ACLK_2

K5

ACLK_2

Clock

Input 3.072MHz audio clock for Audio Group 2 (channels 5-8).

K6

AIN_3/4

Synchronous Input Serial Audio Input; Channels 3 and 4.

with ACLK_1

K7

ACLK_1

Clock

Input 3.072MHz audio clock for Audio Group 1(channels 1-4).

K9

CS_TMS

Synchronous Input COMMUNICATION SIGNAL INPUT

with

Signal levels are LVCMOS/LVTTL compatible.

SCLK_TCK

Chip Select / Test Mode Start.

Host Mode (JTAG/HOST = LOW)

CS_TMS operates as the host interface chip select, CS, and is active

LOW.

JTAG Test Mode (JTAG/HOST = HIGH)

CS_TMS operates as the JTAG test mode start, TMS, used to control

the operation of the JTAG test, and is active HIGH.

NOTE: If the host interface is not being used, tie this pin HIGH.

K10

SDIN_TDI

Synchronous Input COMMUNICATION SIGNAL INPUT

with

Signal levels are LVCMOS/LVTTL compatible.

SCLK_TCK

Serial Data In / Test Data Input

Host Mode (JTAG/HOST = LOW)

This pin operates as the host interface serial input, SDIN, used to write

address and configuration information to the internal registers of the

device.

JTAG Test Mode (JTAG/HOST = HIGH)

This pin is used to shift and operates as the JTAG test data input, TDI.

NOTE: If the host interface is not being used, tie this pin HIGH.

40117 - 1 November 2007

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