HD6433028TE 查看數據表（PDF） - Renesas Electronics

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HD6433028TE

16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Renesas Electronics 

Item

7.4.8 DMAC Bus

Cycle

Figure 7.17 Timing of

DMAC Activation by

Low DREQ Level in

Normal Mode

Page

233

Revision (See Manual for Details)

Figure amended

CPU cycle

DMAC cycle

CPU cycle

T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T 1

φ

DREQ

Address

bus

RD

Figure 7.18 Timing of 234

DMAC Activation by

Falling Edge of DREQ

in Block Transfer Mode

HWR , LWR

Minimum 4 states

Figure amended

Next sampling point

End of 1 block transfer

φ

DREQ

DMAC cycle

CPU cycle

DMAC cycle

T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Td T1 T2

Address

bus

RD

HWR , LWR

7.4.9 Multiple-Channel 236

Operation

Figure 7.19 Timing of

Multiple-Channel

Operations

TEND

Next sampling

Minimum 4 states

Figure amended

DMAC cycle

(channel 1)

CPU

cycle

DMAC cycle

(channel 0A)

CPU

cycle

DMAC cycle

(channel 1)

T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2

φ

Address

bus

RD

HWR ,

LWR

Rev. 2.00, 09/03, page ix of xxx

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