HD74LS175RPEL 查看數據表（PDF） - Renesas Electronics
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HD74LS175RPEL Datasheet PDF : 9 Pages
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HD74LS174 / HD74LS175
Pin Arrangement
HD74LS174
HD74LS175
Clear 1
1Q 2
1D 3
2D 4
2Q 5
3D 6
3Q 7
GND 8
Q CLR
D CK
D CK
Q CLR
D CK
Q CLR
CLR Q
CK D
CK D
CLR Q
CK D
CLR Q
16 VCC
15 6Q
14 6D
13 5D
12 5Q
11 4D
10 4Q
9 Clock
Clear 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
Q
CLR
CK
Q
D
Q
D
CK
Q CLR
CLR Q
CK
D
Q
D
Q
CK
CLR Q
16 VCC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 Clock
(Top view)
(Top view)
Function Table
Inputs
Outputs
Clear
Clock
D
Q
Q
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. Q0; the level of Q before the indicated steady-state input conditions were established.
4. Q is applied to HD74LS175 only.
Rev.3.00, Jul.15.2005, page 2 of 8
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