HD74LS375FPEL 查看數據表（PDF） - Renesas Electronics

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产品描述 (功能)

比赛名单

HD74LS375FPEL

Quadruple Bistable Latches

Renesas Electronics 

HD74LS375

Testing Method

Test Circuit

DG

VCC Q Q

P.G.

Zout = 50Ω

P.G.

Zout = 50Ω

DQ

GQ

CL

RL

RL

CL

Notes:

1. Test is put into the each latch.

2. CL includes prove and jig capacitance.

3. All diodes are 1S2074(H).

Waveform

Notes:

tTLH

1µs

tTHL

1µs

90%

90%

3V

D

1.3 V

1.3 V

1.3 V

10%

10%

tsu

tTLH

th

tTHL

tsu

th

0V

90% 90%

3V

G

1.3 V 1.3 V

1.3 V 1.3 V

10% 10%

0V

500ns

tPLH

tPLH

500ns

tPHL

tPHL

Q

VOH

1.3 V

1.3 V

tPLH

VOL

Q

1.3 V

tPHL

tPHL

tPLH

1.3 V

VOH

VOL

1. Input pulse; D input: PRR = 500 kHz, G input: PRR = 1 MHz, tTHL ≤ 10 ns, tTLH ≤ 10 ns.

2. When measuring propagation delay times from the D input, the corresponding G input must be

held high.

Rev.2.00, Feb.18.2005, page 4 of 5

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