HD74LS280FPEL 查看數據表（PDF） - Renesas Electronics

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HD74LS280FPEL

9-bit Odd / Even Parity Generator / Checker

Renesas Electronics 

HD74LS280

Testing Method

Test Circuit

4.5V

P.G.

Zout = 50Ω

Input

VCC Output

Load circuit 1

A

RL

B

Σ

C

even

D

CL

E

F

G

Output

H

Σ

odd

Same as Load Circuit 1.

I

Notes: 1. CL includes probe and jig capacitance.

2. All diodes are 1S2074(H).

Waveform

tTLH

tTHL

90%

90%

3V

Input

1.3 V

1.3 V

10%

10%

0V

tPLH

tPHL

In phase output

1.3 V

tPHL

1.3 V

tPLH

VOH

VOL

Out of phase output

1.3 V

1.3 V

VOH

VOL

Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%.

Rev.3.00, Jul.15.2005, page 4 of 5

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