HD74LS373FPEL 查看數據表（PDF） - Renesas Electronics
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HD74LS373FPEL Datasheet PDF : 8 Pages
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HD74LS373
Octal D-type Transparent Latches (with three-state outputs)
REJ03D0482–0200
Rev.2.00
Feb.18.2005
The HD74LS373, 8-bit register features totem-pole three-state outputs designed specifically for driving highly-
capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive
provide this register with the capacity of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working registers.
The eight latches are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the
data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was setup.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS373P
DILP-20 pin
PRDP0020AC-B
P
(DP-20NEV)
HD74LS373FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
PRSP0020DC-A
HD74LS373RPEL SOP-20 pin (JEDEC) (FP-20DBV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Pin Arrangement
Output
Control
1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
Q
OE
GD
GD
OE Q
Q
OE
GD
GD
OE Q
OE Q
GD
GD
OE Q
OE Q
GD
GD
OE Q
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 Enable G
(Top view)
Rev.2.00, Feb.18.2005, page 1 of 7
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