HD74LVC1G97CLE 查看數據表（PDF） - Renesas Electronics
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HD74LVC1G97CLE Datasheet PDF : 11 Pages
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HD74LVC1G97
Logic Configurations
VCC
A
1 (IN1) (IN2) 6
A/B
A/B
A
B
Y
2 (GND) (VCC) 5
B
3 (IN0)
(Y) 4
Y
Figure 1. 2 to 1 Data Selecter
VCC
A
B
Y
1 (IN1) (IN2) 6
A
A
B
A
B
2 (GND) (VCC) 5
Y
B
3 (IN0)
(Y) 4
Y
A
B
Figure 2. 2–inputs AND Gate
VCC
A
B
B
1 (IN1) (IN2) 6
A
Y
A
B
A
2 (GND) (VCC) 5
A
B
Y
3 (IN0)
(Y) 4
Y
B
Figure 4. 2–inputs AND Gate
with A input inverted
VCC
1 (IN1) (IN2) 6
A
A
Y
2 (GND) (VCC) 5
A
3 (IN0)
(Y) 4
Y
Figure 6. Inverter
VCC
1 (IN1) (IN2) 6
A
Y
2 (GND) (VCC) 5
Y
B
3 (IN0) (Y) 4
Y
Figure 3. 2–inputs OR Gate
with A input inverted
VCC
B
1 (IN1) (IN2) 6
A
Y
2 (GND) (VCC) 5
Y
3 (IN0)
(Y) 4
Y
Figure 5. 2–inputs OR Gate
VCC
A
1 (IN1) (IN2) 6
Y
2 (GND) (VCC) 5
3 (IN0) (Y) 4
Y
Figure 7. Non–Invert Butter
Rev.4.00 Jun. 29, 2004 page 4 of 10
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