GLT481L16-30TC 查看數據表（PDF） - G-Link Technology
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GLT481L16-30TC Datasheet PDF : 17 Pages
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G-LINK
GLT440L16
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug. 2000 (Rev.1.1)
Truth Table: GLT440L16
Function
RAS
Stanby
H
Read: Word
L
Read: Lower Byte
L
Read: Upper Byte
L
Write: Word(Early
L
Write)
Write: Lower Byte
L
(Early)
Write: Upper Byte
L
(Early)
Read Write
L
EDO-Page- 1st Cycle
L
Mode Read 2nd Cycle
L
CASL CASH WE
H
H
X
L
L
H
L
H
H
H
L
H
L
L
L
OE ADDRESS
DQs
Notes
X
High-Z
L ROW/COL Data Out
L ROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
L ROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
X ROW/COL Data-In
L
H
L
X ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
H
L
L
X ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
L
L H→L L→H ROW/COL Data-Out,Data-In
1,2
H→L H→L H
L ROW/COL Data-Out
2
H→L H→L H
L
COL Data-Out
2
EDO-Page- 1st Cycle
L
H→L H→L L
X ROW/COL Data-In
2
Mode Write 2nd Cycle
L
H→L H→L L
X
COL Data-In
2
EDO-Page- 1st Cycle
Mode Read-
L
H→L H→L H→L L→H ROW/COL Data-Out,Data-In
1,2
Write
2nd Cycle
L
H→L H→L H→L L→H
COL Data-Out,Data-In
1,2
Hidden
Read
L→H→L L
L
H
L ROW/COL Data-Out
2
Refresh
Write
L→H→L L
L
H
L ROW/COL Data-In
2
RAS -Only Refresh
L
H
H
X
X
ROW High-Z
CBR Refresh
H→L
L
L
X
X
High-Z
3
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active).
2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation
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Santa Clara, CA 95051, U.S.A.
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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