HT7627 查看數據表（PDF） - Holtek Semiconductor
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HT7627 Datasheet PDF : 6 Pages
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The operation will be explained with reference to the following diagrams:
i2
L
SD
V IN
i1
tr
CL
HT7627
IO U T
V OUT
IL
IL m a x
to p e n
I L m in
t
to n
t ff
t= 1 /fO S C
Step1: tr is turned ON and current IL (=i1) flows, so that energy is charged in L. At this moment, IL (=i1) is increased
from ILmin to reach ILmax in proportion to the on-time period (ton) of tr.
Step2: When tr is turned OFF, Schottky diode (SD) is turned ON in order that L maintains IL at ILmax, so that current IL
(=i2) is released.
Step3: IL (=i2) is gradually decreased, IL reaches ILmin after a time period of topen, so that SD is turned OFF. tr will be
turned ON in the next cycle.
In the case of PWM control system, the output voltage is maintained constant by controlling the on-time period (ton),
with the oscillator frequency (fOSC) being maintained constant.
Voltage detector operation
The HT7627 built-in voltage detector is equipped with a high stability voltage reference which is connected to the nega-
tive of a comparator ¾ denoted as Vref in the following figure for NMOS output voltage detector.
When the voltage drop to the positive input of the comparator (i.e. VB) is higher than Vref, VOUT goes high, and VB is ex-
pressed as VBH=VDD ´ (RB+RC) / (RA+RB+RC). If VDD is decreased so that VB falls to a value less than Vref, the com-
parator output inverts from high to low, VOUT goes low, VC is high, RC is bypassed, and VB becomes: VBL=VDD ´
RB/(RA+RB), which is less than VBH. By so doing, the comparator output will remain low to prevent the circuit from oscil-
lating when VB»Vref.
If VDD falls below the minimum operating voltage, the output becomes undefined. When VDD goes from low to VDD ´ RB
/ (RA+RB) > Vref, the comparator output and VOUT goes high. The detectable voltage is defined as:
VDETECT
(-)=
RA + RB + RC
RB + RC
´
Vref
The release voltage is defined as:
VDETECT
(+)=
RA
+
RB
RB
+
RC
´
Vref
Rev. 1.00
3
January 18, 2002
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