1527G1LF 查看數據表（PDF） - Integrated Circuit Systems

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1527G1LF

Video Clock Synthesizer

Integrated Circuit Systems 

ICS1527 Data Sheet

Section 1 Overview

The ICS1527 is a user-programmable,

high-performance general purpose clock generator. It

is intended for graphics system line-locked and

genlocked applications, and provides the clock signals

required by high-performance analog-to-digital

converters.

Figure 1-1 Simplified Block Diagram

Section 1 Overview

The ICS1527 has the ability to operate in line-locked

mode with the HSYNC input.

1.1 Phase-Locked Loop

The phase-locked loop has a very wide input frequency

range (8 kHz to 100 MHz). Not only is the ICS1527 an

excellent, general purpose clock synthesizer, but it is

also capable of line-locked operation. Refer to the

block diagram below.

HSYNC

CP

VCO VCOD

PFD

2,4,8,16

FD

12..4103

CLK

EXTFB

VSYNC

Flip-flop

Flip-flop

HSYNC_out

VSYNC_out

Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity

The heart of the ICS1527 is a voltage controlled

oscillator (VCO). The VCO speed is controlled by the

voltage on the loop filter. This voltage will be described

later in this section.

The VCO’s clock output is first passed through the

VCO Divider (VCOD). The VCOD allows the VCO to

operate at higher speeds than the required output

clock.

NOTE: Under normal, locked operation the VCOD has

no effect on the speed of the output clocks, just the

VCO frequency.

The output of the VCOD is the full speed output

frequency seen on the CLK. This clock is then sent

through the 12-bit internal Feedback Divider (FD). The

feedback divider controls how many clocks are seen

during every cycle of the input reference.

The Phase Frequency Detector (PFD) then compares

the feedback to the input and controls the filter voltage

by enabling and disabling the charge pump. The

charge pump has programmable current drive and will

source and sink current as appropriate to keep the

input and the HSYNC_out output aligned.

The input HSYNC and VSYNC can be conditioned by a

high-performance Schmitt-trigger by sharpening the

rising/falling edge.

The HSYNC_out and VSYNC_out signals are aligned

with the output clock (CLK) via a set of flip flops.

1.2 Output Drivers and Logic Inputs

The ICS1527 uses low-voltage TTL (LVTTL) inputs and

LVCMOS outputs, operating at the 3.3 V supply

voltage. The LVTTL inputs are 5 V tolerant.

The LVCMOS drive resistive terminations or

transmission lines.

1.3 Automatic Power-On Reset Detection

The ICS1527 has automatic power-on reset detection

(POR) circuitry and it resets itself if the supply voltage

drops below threshold values. No external connection

to a reset signal is required.

MDS 1527 G

2

Revision 110905

Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com

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