Recommended Circuit:
S1
VDD
GND
INPUT
S0
FBIN
ICS570A
Multiplier and Zero Delay Buffer
CLK
CLK/2
ICLK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
ICK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. But the
CLK/2 could be a falling edge compared with ICLK. Therefore, wherever possible, we recommend the use of
CLK/2 feedback. This will synchronize the rising edges of all 3 clocks.
MDS 570A C
5
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com