ICS9112-18 查看數據表（PDF） - Integrated Circuit Systems

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产品描述 (功能)

比赛名单

ICS9112-18

Zero Delay, Low Skew Buffer

Integrated Circuit Systems 

Pin Assignment

ICS9112-18

CLKIN 1

CLKA1 2

CLKA2 3

VDD 4

GND 5

CLKB1 6

CLKB2 7

16 FBIN

15 CLKA4

14 CLKA3

13 VDD

12 GND

11 CLKB4

10 CLKB3

S2 8 9 S1

16 pin narrow (150 mil) SOIC

ICS9112-18

Zero Delay, Low Skew Buffer

Feedback Configuration Table

Feedback From

Bank A

Bank B

CLKA1:A4

CLKIN

2XCLKIN

CLKB1:B4

CLKIN/2

CLKIN

Output Clock Mode Select Table

S2

S1

Clocks A1-A4

Clocks B1-B4

Internal Generation

0

0 Tri-state (high impedance) Tri-state (high impedance)

None

0

1

Running

Tri-state (high impedance)

PLL

1

0

Running

Running

Buffer Only (no zero delay)

1

1

Running

Running

PLL

PLL Status

On

On

Off

On

Pin Descriptions

Number

1

2, 3, 14, 15

4, 13

5, 12

6, 7, 10, 11

8

9

16

Name

CLKIN

CLKA1:4

VDD

GND

CLKB1:4

S2

S1

FBIN

Type

I

O

P

P

O

I

I

I

Description

CLocK INput. Connect to input clock source.

CLocK A bank of four outputs.

Power supply. Connect both pins to same voltage (either 3.3V or 5V).

Connect to ground.

CLocK B bank of four outputs. These are low skew divide by two of bank A.

Select input #2. Selects mode for outputs per table above.

Select input #1. Selects mode for outputs per table above.

FeedBack INput. Determines outputs per Feedback Configuration Table above.

Key: I = Input; O = output; P = power supply connection.

External Components

The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND

on pins 13 and 12, as close to the device as possible. A series termination resistor of 33 Ω may be used close

to the pin for each clock output to reduce reflections.

MDS 9112-18 F

2

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

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