ICS9250-28 查看數據表（PDF） - Integrated Circuit Systems

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产品描述 (功能)

比赛名单

ICS9250-28

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

Power Down Waveform

ICS9250-28

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Maximum Allowed Current

815

Condition

Powerdown Mode

(PWRDWN# = 0

Full Active 66MHz

FS[2:0] = 010

Full Active 100MHz

FS[2:0] = 011

Full Active 133MHz

FS[2:0] = 111

Max 2.5V supply consumption Max 2.5V supply consumption

Max discrete cap loads,

Max discrete cap loads,

Vddq2 = 2.625V

Vddq2 = 3.465V

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

10mA

10mA

70mA

400mA

100mA

400mA

130mA

450mA

Clock Enable Configuration

PD# CPUCLK SDRAM IOAPIC

66MHz

PCICLK

REF,

48MHz

Osc

VCOs

0

LOW

LOW LOW LOW LOW LOW OFF OFF

1

ON

ON

ON

ON

ON

ON ON ON

3

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