IDT2309(2012) 查看數據表（PDF） - Integrated Device Technology
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IDT2309 Datasheet PDF : 10 Pages
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IDT2309
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
16 CLKOUT
15 CLKA4
14 CLKA3
13
VDD
12
GND
11
CLKB4
10
CLKB3
9
S1
SOIC/ TSSOP
TOP VIEW
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD) ContinuousOutputCurrent
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
Operating
Industrial Temperature
-40 to +85 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF
CLKA1(1)
CLKA2(1)
VDD
GND
CLKB1(1)
CLKB2(1)
S2(2)
S1(2)
CLKB3(1)
CLKB4(1)
CLKA3(1)
CLKA4(1)
CLKOUT(1)
Pin Number
1
2
3
4, 13
5, 12
6
7
8
9
10
11
14
15
16
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
Type
Functional Description
IN
Input reference clock, 5 Volt tolerant input
Out
Output clock for bank A
Out
Output clock for bank A
PWR
3.3V Supply
GND
Ground
Out
Output clock for bank B
Out
Output clock for bank B
IN
Select input Bit 2
IN
Select input Bit 1
Out
Output clock for bank B
Out
Output clock for bank B
Out
Output clock for bank A
Out
Output clock for bank A
Out
Output clock, internal feedback on this pin
2
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