IDT49FCT805BT/CT 查看數據表（PDF） - Integrated Device Technology
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IDT49FCT805BT/CT Datasheet PDF : 7 Pages
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IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805BT/806BT IDT49FCT805CT/806CT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
tPLH Propagation Delay
tPHL INA to OAn, INB to OBn
tR
Output Rise Time
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
1.5
—
Max.
5.0
1.5
Min.(2)
1.5
—
Max.
5.7
2.0
Min.(2)
1.5
—
Max.
4.5
1.5
Min.(2)
1.5
—
Max.
5.2
2.0
Unit
ns
ns
tF
Output Fall Time
— 1.5 — 1.5 — 1.5 — 1.5 ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together)
— 0.7 — 0.9 — 0.5 — 0.7 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL–t PLH|)
— 0.7 — 0.9 — 0.6 — 0.8 ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.2 — 1.5 — 1.0 — 1.2 ns
tPZL Output Enable Time
tPZH OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
tPLZ Output Disable Time
tPHZ OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
NOTES:
2920 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.2
5
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