IDT74FCT540TDB 查看數據表（PDF） - Integrated Device Technology
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IDT74FCT540TDB Datasheet PDF : 9 Pages
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IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500Ω
500Ω
7.0V
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2565 drw 14
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2565 drw 10
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2565 drw 11
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
tW
1.5V
2565 drw 12
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
25605 Vdrw 13
ENABLE
DISABLE
3V
CONTROL
INPUT
tPZL
1.5V
0V
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
3.5V
1.5V
tPHZ
3.5V
0.3V VOL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0.3V VOH
0V
2565 drw 14
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.8
8
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