IDT7008L(2018) 查看數據表（PDF） - Integrated Device Technology
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IDT7008L Datasheet PDF : 20 Pages
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HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT7008S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/55ns (max.)
◆ Low-power operation
– IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
Functional Block Diagram
R/WL
CE0L
CE1L
OEL
R/WR
CE0R
CE1R
OER
I/O0-7L
I/O
Control
I/O
Control
BUSYL(1,2)
A15L
A0L
Address
Decoder
16
CE0L
CE1L
OEL
R/W L
64Kx8
MEMORY
ARRAY
7008
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S(1)
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2018 Integrated Device Technology, Inc.
Address
Decoder
CE0R
CE1R
OER
R/WR
I/O0-7R
BUSYR(1,2)
A15R
A0R
SEMR
INT
(2)
R
3198 drw 01
MARCH 2018
DSC 3198/12
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