IDT7024 查看數據表（PDF） - Integrated Device Technology
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IDT7024 Datasheet PDF : 22 Pages
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HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
IDT7024S/L
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆ Low-power operation
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆ IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆ M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Battery backup operation—2V data retention
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts availble, see ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL(1,2)
I/O
Control
I/O
Control
A11L
A0L
Address
Decoder
12
CEL
OEL
R/WL
MEMORY
ARRAY
12
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2008 Integrated Device Technology, Inc.
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR(1,2)
A11R
A0R
SEMR
INTR(2)
2740 drw 01
OCTOBER 2008
DSC 2740/13
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