IDT7099S 查看數據表（PDF） - Integrated Device Technology
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IDT7099S Datasheet PDF : 9 Pages
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IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE
tCYC
CLK
tCH
tCL
tSCK
tHCK
tSCK
CLKEN
tS
tH
CE
W BYTE R/
W or BIT R/
ADDRESS
An
An + 1
An + 2
tCD
tDC
DATAOUT
Qn
tCKLZ(1)
Qn + 1
tOHZ(1)
BYTE OE
or BIT OE
NOTE:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
An + 3
tCKHZ(1)
Qn + 1
tOLZ (1)
tOE
3007 drw 08
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1,2,3)
CLK "A"
W R/ "A"
(4)
ADDR "A"
MATCH
NO
MATCH
DATAIN "A"
VALID
CLK "B"
W R/ "B"
ADDR "B"
MATCH
tCWDD
NO
MATCH
tCD
DATAOUT "B"
VALID
NOTES:
tDC
1. CEL = CER = VIL, CLKENL = CLKENR = VIL
2. OE = VIL for the reading port, port 'B'.
3. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
4. W R/ 'A' was active (VIL) during the previous CLK'A', when enabled the write path.
VALID
3007 drw 09
6.23
6
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