IDT71128S12Y 查看數據表（PDF） - Integrated Device Technology

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IDT71128S12Y

CMOS Static RAM 1 Meg (256K x 4-Bit) Revolutionary Pinout

Integrated Device Technology 

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)

tWC

ADDRESS

tAW

CS

WE

DATAOUT

DATAIN

tAS

tWP (2)

tWR

tWHZ (5)

tOW (5)

(3)

HIGH IMPEDANCE

tDW

tDH

DATAIN VALID

tCHZ (5)

(3)

3483 drw 07

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)

ADDRESS

CS

tAS

WE

DATAIN

tWC

tAW

tCW

tWR

tDW

tDH

DATAIN VALID

3483 drw 08

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period.

5. Transition is measured ±200mV from steady state.

6.462

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