IDT71321 查看數據表（PDF） - Integrated Device Technology
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IDT71321 Datasheet PDF : 13 Pages
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IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TRUTH TABLES
COMMERCIAL TEMPERATURE RANGE
TABLE I —
NON-CONTENTION READ/WRITE CONTROL(4)
Left or Right Port(1)
R/W CE OE D0–7
Function
XH X
Z Port Disabled and in Power-
Down Mode, ISB2 or ISB4
XH X
Z
CER = CEL = VIH, Power-Down
Mode, ISB1 or ISB3
L L X DATAIN Data on Port Written Into Memory(2)
H L L DATAOUT Data in Memory Output on Port(3)
HL H
Z High-impedance Outputs
NOTES:
2654 tbl 13
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = VIL, data is not written.
3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
TABLE II — INTERRUPT FLAG(1,4)
R/WL
L
X
X
X
Left Port
CEL OEL
L
X
X
X
X
X
L
L
A10L – A0L
7FF
X
X
7FE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE.
INTL
X
X
L(3)
H(2)
R/WR
X
X
L
X
Right Port
CER OER A10L – A0R
X
X
X
L
L
7FF
L
X
7FE
X
X
X
INTR
L(2)
H(3)
X
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2654 tbl 14
TABLE III — ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A10L
CEL CER A0R-A10R BUSYL(1) BUSYR(1)
Function
X
X NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
L
L
MATCH
(2)
H
Normal
(2)
Write Inhibit(3)
NOTES:
2689 tbl 15
1. Pins BUSYL and BUSYR are both outputs for IDT71321 (master). Both are
inputs for IDT71421 (slave). BUSYX outputs on the IDT71321 are open
drain, not push-pull outputs. On slaves the BUSYX input internally inhibits
writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs
can not be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving Low regard-
less of actual logic level on the pin.
6.03
11
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