IDT723674 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

比赛名单

IDT723674

CMOS SyncBiFIFO™ WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

Integrated Device Technology 

IDT723654/723664/723674 CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Commercial

IDT723654L12 IDT723654L15

IDT723664L12 IDT723664L15

IDT723674L12 IDT723674L15

Symbol

fS

tCLK

tCLKH

tCLKL

tDS

tENS1

tENS2

tRSTS

tFSS

tBES

tSDS

tSENS

tFWS

tRTMS

tDH

tENH

tRSTH

tFSH

tBEH

tSDH

tSENH

tSPH

tRTMH

tSKEW1(2)

tSKEW2(2.3)

Parameter

Clock Frequency, CLKA or CLKB

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA or CLKB HIGH

Pulse Duration, CLKA and CLKB LOW

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑

Setup Time, ENA, and MBA before CLKA↑; ENB, and MBB before CLKB↑

Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑(1)

Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Setup Time, BE/FWFT before CLKA↑

Setup Time, RTM before RT1; RTM before RT2

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and

MBB after CLKB↑

Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑(1)

Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

Hold Time, FS0/SD after CLKA↑

Hold Time, FS1/SEN HIGH after CLKA↑

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

Hold Time, RTM after RT1; RTM after RT2

Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA,

and FFB/IRB

Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB

Min. Max. Min. Max. Unit

—

83

— 66.7 MHz

12

—

15 —

ns

5

—

6—

ns

5

—

6—

ns

3

—

4—

ns

4

—

4.5 —

ns

3

—

4.5 —

ns

5

—

5—

ns

7.5

—

7.5 —

ns

7.5

—

7.5 —

ns

3

—

4—

ns

3

—

4—

ns

0

—

0—

ns

5

—

5—

ns

0.5

—

1—

ns

0.5

—

1—

ns

4

—

4—

ns

2

—

2—

ns

2

—

2—

ns

0.5

—

1—

ns

0.5

—

1—

ns

2

—

2—

ns

5

—

5—

ns

5

—

7.5 —

ns

12

—

12 —

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

3. Design simulated, not tested.

4. Industrial temperature range is available by special order.

9

Share Link: