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IDT74FCT237ATP 查看數據表(PDF) - Integrated Device Technology

零件编号
产品描述 (功能)
比赛名单
IDT74FCT237ATP
IDT
Integrated Device Technology IDT
IDT74FCT237ATP Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT373T/2373T/573T/2573T FCT373AT/2373AT/573AT/2573AT
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
Parameter
Propagation Delay
DN to ON
Propagation Delay
LE to ON
Output Enable Time
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
Conditions(1)
CL = 50pF
RL = 500
Com'l.
Min.(2) Max.
1.5 8.0
Mil.
Min.(2) Max.
1.5 8.5
Com'l.
Min.(2) Max.
1.5 5.2
Mil.
Min.(2) Max. Unit
1.5 5.6 ns
2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns
1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns
1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns
2.0 — 2.0 — 2.0 — 2.0 — ns
1.5 — 1.5 — 1.5 — 1.5 — ns
6.0 — 6.0 —
FCT373CT/2373CT/573CT/2573CT
5.0 — 6.0
FCT373DT/573DT
— ns
2564 tbl 10
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
Parameter
Propagation Delay
DN to ON
Propagation Delay
LE to ON
Output Enable Time
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH(3)
Conditions(1)
CL = 50pF
RL = 500
Com'l.
Min.(2) Max.
1.5 4.2
Mil.
Min.(2) Max.
1.5 5.1
Com'l.
Min.(2) Max.
1.5 3.8
Mil.
Min.(2) Max.
Unit
ns
2.0 5.5 2.0 8.0 2.0 4.0 —
— ns
1.5 5.5 1.5 6.3 1.5 4.8 —
— ns
1.5 5.0 1.5 5.9 1.5 4.0 —
— ns
2.0 — 2.0 — 1.5 —
— ns
1.5 — 1.5 — 1.0 —
— ns
5.0 — 6.0 — 3.0 —
— ns
2564 tbl 11
FCT533T
FCT533AT
FCT533CT
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay
tPHL
DN to ON
CL = 50pF 1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns
RL = 500
tPLH Propagation Delay
tPHL
LE to ON
2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns
tPZH Output Enable
tPZL
Time
1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
tPHZ Output Disable
tPLZ
Time
1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns
tSU
Set-up Time HIGH
or LOW, DN to LE
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns
tH
Hold Time HIGH
or LOW, DN to LE
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
tW
LE Pulse Width HIGH
6.0 — 6.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
— 5.0
— 6.0
— 5.0
— 6.0
— ns
2564 tbl 12
6.12
6

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