IDT7M1003 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

比赛名单

IDT7M1003

128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

Integrated Device Technology 

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)

t OH

t AA

A0 - A2

VALID ADDRESS

VALID ADDRESS

SEM

t AW

t WP

t WR

t DW

t SOP

t ACS

DATA 0

R/W

DATA IN VALID

t AS

t WP

t DH

t OE

t SWRD

OE

t SOP

WRITE CYCLE

READ CYCLE

NOTE:

1. CS = HIGH for the duration of the above timing (both write and read cycle).

DATAOUT

VALID

2804 drw 10

TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)

A 0A - A 2A

MATCH

SIDE (2) “A”

R/W A

SEM A

A 0B - A 2B

SIDE(2) “B”

R/WB

t SPS

MATCH

SEM B

NOTES:

1. D0R = D0L = LOW, L_CS = R_CS = HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.

2. "A" may be either left or right port. "B" is the opposite port from "A".

3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.

4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

2804 drw 11

7.5

8

Share Link: